1. Field of the Invention
The present invention relates generally to the field of computer systems, and in particular to methods and mechanisms for maintaining order among memory transactions.
2. Description of the Related Art
A system on chip (SoC) often includes multiple input/output (I/O) devices and a processor sharing one or more memory devices via a memory controller. Many different agents may generate memory transactions and convey these memory transactions to the memory controller. Often, a coherence point is used to maintain the ordering and coherence of these memory transactions within the SoC.
In one embodiment, each transaction received by a coherence point may include a flow-identifier (ID) identifying which flow the transaction is a part of. A flow may be defined as a series of transactions or requests from the same source to the same destination. Transactions with the same flow-ID should be issued out of the coherence point in the order in which they were received. However, the coherence point may store the transactions in a queue which is not a first-in-first-out (FIFO) queue, and so the order of entries in the queue is not an indication of order.